The present invention relates to technology for designing an LSI layout. More particularly, the present invention relates to LSI layout designing technology, in which cells are interchanged in such a manner as to satisfy required specifications about timing, power consumption and the like.
FIG. 16 is a flow chart illustrating the processing procedure of a conventional LSI layout designing method in accordance with standard cell processing.
In input processing S51, required specifications 51 about timing, power consumption and the like, circuit designing information 52 obtained by logical designing and a cell library 53 are input.
FIG. 17 is a schematic representation diagrammatically illustrating the cell library 53 for use in conventional LSI layout designing. In the cell library 53, a plurality of cells having such logic functions as required for operating an LSI are provided. Among these cells, there are some cells having equivalent logic but different transistor sizes, i.e., different levels of drivability (e.g., output current and output voltage).
In conventional standard cell processing in general, a restriction is imposed on cells that the cells have an equal height. On the other hand, no restriction is imposed on the widths of the cells, which may be set at arbitrary values. Accordingly, when there are cells having equivalent logic and mutually different levels of drivability, a cell having a larger level of drivability tends to be designed to have a larger cell width.
In FIG. 17, cells 61A, 61B and 61C are logically equivalent cells (implemented as inverters), the levels of drivability of which increase in the order of 61A less than 61B less than 61C. More specifically, the cells 61A, 61B and 61C have an equal height but mutually different widths, which increase in the order of 61A less than 61B less than 61C. Similarly, cells 62A, 62B, and 62C are logically equivalent cells (implemented as two-input AND gates), the levels of drivability of which increase in the order of 62A less than 62B less than 62C. Similarly, the cells 62A, 62B and 62C also have an equal height but mutually different widths, which increase in the order of 62A less than 62B less than 62C.
Referring back to FIG. 16, in arrangement processing S52, a plurality of cells are selected from the cell library 53 and two-dimensionally arranged in parallel on a plane based on the circuit designing information 52. Then, a block layout, including a plurality of cell rows arranged in parallel, is designed. In routing processing S53, the cells are wired with each other based on the circuit designing information 52.
FIG. 18A illustrates an exemplary block layout designed in accordance with the arrangement processing S52 and the routing processing S53. As shown in FIG. 18A, three cell rows 73a, 73b and 73c are arranged in a block 70. Each of the rows 73a, 73b and 73c includes a plurality of cells 71. The reference numeral 72 denotes a terminal of the cell 71 and the reference numeral 74 denotes a wire connecting two terminals 72 together. If complete routing cannot be performed only over on-cell regions (i.e., areas directly above the cells), then pure wiring regions 75a and 75b dedicated entirely for wiring are provided between adjacent rows, and the routing is completed by using these regions 75a and 75b. 
FIG. 16 will be referred to again. In cell-in-question extraction processing S54, a cell including a circuit section failing to satisfy the required specifications is extracted as a cell to be interchanged with an appropriate cell (in this specification, such a cell will be referred to as a xe2x80x9ccell in questionxe2x80x9d). Herein, assume a delay restriction is imposed on each net. Then, the delay time of each net is calculated based on the delay parameter information of a cell driving the net and a cell at the next stage, which both are included in the cell library 53, and on the routing results of the routing processing S53. If the calculated delay time fails to satisfy the delay restriction, then the cell driving the net is extracted as a cell in question. As shown in FIG. 18A, the cell in question is identified by hatching, i.e., a cell 76A.
In drivability calculation processing S55, it is calculated what level of drivability is required for the cell in question, which has been extracted through the cell-in-question extraction processing S54, to satisfy the required specifications.
The delay time Td of a net is given by the following equation:
Td=Tin+Tld+Tw+Tpxe2x80x83xe2x80x83(1)
where Tin denotes gate intrinsic delay, Tld denotes an over-all load (i.e., a sum of wiring capacitance and the capacitance of the input terminal of a gate on the next stage), Tw denotes wiring delay and Tp denotes delay dependent on the blurred waveform (i.e., a signal having rising and falling edges exhibiting a less sharp shape than the previous signal) of the previous stage.
If the drivability of a cell is varied, then the gate intrinsic delay Tin and the overall load Tld vary but the wiring delay Tw and the delay Tp dependent on the blurred waveform of the previous stage do not vary. The wiring delay Tw is calculated based on the routing designed in accordance with the routing processing S53. By using this equation, the drivability of a cell is calculated in such a way that the delay time Td of a net satisfies the restriction thereof.
In cell interchange processing S56, the cell in question is replaced with a cell having such a level of drivability as calculated in accordance with the drivability calculation processing S55.
The conventional LSI layout designing supposes the use of a cell library 53 such as that shown in FIG. 17. Thus, if a cell in question is interchanged with a cell having a larger level of drivability, then the substitute cell sometimes overlaps with an adjacent cell, because the cell has a larger cell width. Conversely, if a cell in question is interchanged with a cell having a smaller level of drivability, then a gap is unintentionally produced between the substitute cell and an adjacent cell. In order to eliminate such overlap and gap, some cells belonging to the same row need to be relatively moved in the cell row direction. However, if the cells are moved in such a manner, the terminal positions of the cells are also moved to deviate from the originally intended positions determined in the routing processing S52.
FIG. 18B shows a resultant arrangement in which the cell in question 76A shown in FIG. 18A has been interchanged with a logically equivalent cell 76B having a larger level of drivability. Since the cell 76B has a width larger than that of the cell 76A, the cells located on the right-hand side of the cell 76B on the same row 73b need to be moved to the right in order to prevent the cell 76B from overlapping the adjacent cell. As a result, the positions of the terminals 72 shown in FIG. 18B have also changed by comparison with FIG. 18A. Also, since the cell row 73b becomes longer than that of any other row 73a, 73c, the resultant width of the block 70 increases and dead spaces, where no cells are disposed, are produced on the right-hand side of the rows 73a and 73c. The cell-in-question extraction processing S54, the drivability calculation processing S55 and the cell interchange processing S56 are disclosed, for example, in Shen Lin et al., xe2x80x9cDelay and Area optimization in Standard-Cell Designxe2x80x9d, 1990 Design Automation Conference, which is herein incorporated by reference.
Referring back to FIG. 16, in re-routing processing S57, routing is performed again with respect to the terminals moved to different positions. FIG. 18B also shows the results of the re-routing processing S57. As can be understood from the comparison between FIGS. 18A and 18B, the wiring routes have also changed. In this case, the height of the block 70 sometimes changes as a result of the re-routing processing S57.
On the other hand, in accordance with conventional LSI layout designing, circuit designing is once performed by using cells having relatively larger levels of drivability to allow a sufficient margin for timing. Then, by using a delay time obtained after the arranging/routing processing has been performed for the layout designing, some of the cells are interchanged with cells having smaller levels of drivability so as to satisfy the timing requirement and thereby reduce the resulting power consumption.
However, the conventional LSI layout designing has the following problems.
First, as already described, if the cell interchange processing is performed so as to satisfy the required specifications in accordance with the conventional method, then the terminal positions of the cells unintentionally move from those defined in the originally designed arrangement. Thus, re-routing processing needs to be performed, and therefore, the overall processing time of the layout designing becomes adversely lengthy.
In addition, since the wiring routes drastically change as a result of the re-routing processing, an actual wiring delay time greatly deviates from the time estimated for the initial arrangement. In general, the propagation delay time of an LSI is given as a sum of a gate delay time and a wiring delay time. However, as the size of an LSI is miniaturized, the proportion of the wiring delay time to the entire propagation delay time more and more increases. Thus, such an erroneously estimated wiring delay time will cause a non-negligible serious problem.
The wiring delay time is varied as a result of the re-routing processing because of the following two reasons. For one thing, the length of a wire changes. The other factor is variation in wiring capacitance between adjacent wires because the positional interrelation between wires changes owing to the change of the wiring routes.
In particular, the change of the wiring delay time, resulting from the variation in capacitance between adjacent wires, becomes more significant as the size of an LSI is further miniaturized. This is because the proportion of the capacitance between adjacent wires with respect to the entire wiring capacitance tends to increase as an LSI is downsized. Thus, even slight change of the wiring routes brings about drastic change of a wiring delay time.
Owing to the change of the wiring delay time resulting from the variation in capacitance between adjacent wires, it is extremely difficult to secure required specifications such as timing restriction by performing cell interchange processing only once. The rationale is as follows. Even when the drivability of a cell is defined in accordance with Equation (1) so as to satisfy the required specifications, the required specifications are not always satisfied because the wiring delay Tw of Equation (1) changes as a result of the re-routing processing. Thus, redundant processing, such as the repetition of cell interchange processing, needs to be performed. Consequently, the overall processing time of the LSI layout designing disadvantageously increases.
An object of the present invention is to satisfy required specifications in a short processing time with certainty by suppressing change in wiring delay time resulting from cell interchange during LSI layout designing.
Specifically, the LSI layout designing method of the present invention includes a step of interchanging a cell in question with a substitute cell in a block layout including a plurality of cell rows and being designed based on circuit designing information so as to satisfy required specifications. The cell rows are arranged in parallel to each other. In the interchanging step, the cell in question is interchanged with the substitute cell by using a stretchable cell library as a cell library constituting a set of cells to be arranged. Cells in the stretchable cell library, which have equivalent logic and different levels of drivability, are provided with such a cell layout that widths and terminal positions of the cells are equal to each other in a cell arrangement direction on each said row.
According to the present invention, when a cell in question is interchanged with a cell having a required level of drivability for satisfying the required specifications through the cell interchange, the widths and terminal positions in the cell arrangement direction on each cell row do not change before and after the cell interchange. Thus, since the wiring routes used for the block layout before the cell interchange can be used as it is as part of the results of layout designing, there is no need to perform re-routing. In addition, since the positional interrelation between the wires does not change through the cell interchange either, the change in wiring delay time resulting from the cell interchange is considerably smaller as compared with a conventional case. Accordingly, the required specifications can be satisfied by performing a cell interchange only once. Consequently, the required specifications can be satisfied with certainty in a short processing time.
The present invention also provides an LSI layout designing apparatus for implementing the LSI layout designing method.
Moreover, the present invention provides a computer readable recording medium in which a program for implementing the LSI layout designing method is recorded.
Furthermore, the present invention provides a computer readable recording medium in which a stretchable cell library used for implementing the LSI layout designing method is recorded.
Also, the present invention provides a semiconductor integrated circuit designed in accordance with the LSI layout designing method. The semiconductor integrated circuit includes a plurality of cells that are arranged along a pair of power lines. At least part of the cells are formed so as to cover a region between the pair of power lines and regions outside of the region between the power lines. Intra-cell wiring of each said cell is formed in a part of a predetermined wiring layer located in a first on-cell wiring region. The first on-cell wiring region is located in the region between the power lines. Other parts of the predetermined wiring layer, located in second on-cell wiring regions, are used for inter-cell wiring. The second on-cell wiring regions are located in regions outside of the region between the power lines.